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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [rtlsim.sh] - Rev 200

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200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3574d 06h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4577d 17h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4609d 08h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4778d 08h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
99 Small fix for CVER simulator support. olivier.girard 4997d 08h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4997d 08h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5001d 08h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5206d 09h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5366d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
37 olivier.girard 5423d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5423d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
17 Updated header with SVN info olivier.girard 5570d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5605d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh

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