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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_halt_irq.s43] - Rev 154

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154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4433d 08h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.s43
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4596d 07h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4947d 08h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.
olivier.girard 5036d 08h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43

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