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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog] - Rev 143

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Rev	Log message	Author	Age	Path
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4402d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
136	Update all FPGA projects with the latest core version.	olivier.girard	4450d 13h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4757d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4813d 12h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4813d 12h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4832d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4838d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4842d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4923d 21h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/bench/verilog

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