URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_frontend.v] - Rev 107

Rev	Log message	Author	Age	Path
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4838d 12h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4853d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4857d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4871d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
85	Diverse RTL cosmetic updates.	olivier.girard	4894d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4948d 22h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v