URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [smartgen] - Rev 81

Rev	Log message	Author	Age	Path
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	5083d 08h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5083d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/smartgen