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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog] - Rev 86

Rev	Log message	Author	Age	Path
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4909d 13h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
85	Diverse RTL cosmetic updates.	olivier.girard	4909d 15h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4914d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4960d 16h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4963d 14h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4963d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog