URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [bin/] [msp430sim] - Rev 212

Rev	Log message	Author	Age	Path
212	Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains.	olivier.girard	3285d 11h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4498d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4588d 11h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
136	Update all FPGA projects with the latest core version.	olivier.girard	4620d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	5008d 02h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	5093d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim