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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim/] [src] - Rev 111

Rev	Log message	Author	Age	Path
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4781d 02h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4836d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4852d 01h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4947d 09h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/src