OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [sim/] [rtl_sim] - Rev 212

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3122d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4250d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4335d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4425d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
136 Update all FPGA projects with the latest core version. olivier.girard 4457d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4764d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4820d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4835d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4845d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4849d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4927d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4930d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.