URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel] - Rev 155

Rev	Log message	Author	Age	Path
155	Update FPGA projects with the latest openMSP430 verilog code.	olivier.girard	4249d 22h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
136	Update all FPGA projects with the latest core version.	olivier.girard	4456d 22h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4763d 23h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4819d 21h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4927d 00h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4929d 22h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4930d 06h	/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis/actel