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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis] - Rev 155

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4260d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
136 Update all FPGA projects with the latest core version. olivier.girard 4467d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4774d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4830d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories
olivier.girard 4937d 21h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4940d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4941d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/synthesis

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