OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit] - Rev 143

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4430d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4447d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
136 Update all FPGA projects with the latest core version. olivier.girard 4478d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
132 Update FPGA examples with the POP.B bug fix olivier.girard 4491d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4575d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
112 Modified comment. olivier.girard 4784d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4785d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4841d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4841d 17h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4856d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4860d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4866d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4870d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4874d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4897d 16h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
85 Diverse RTL cosmetic updates. olivier.girard 4897d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4902d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4948d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 4948d 19h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4951d 18h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.