URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [driver_7segment.v] - Rev 109

Rev	Log message	Author	Age	Path
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4824d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4845d 07h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5287d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5398d 11h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
16	Updated header with SVN info	olivier.girard	5424d 06h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5459d 06h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v