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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_register_file.v] - Rev 212

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202 Add DMA interface support + LINT cleanup olivier.girard 3302d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
181 Update with latest oMSP Core version. olivier.girard 4158d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
136 Update all FPGA projects with the latest core version. olivier.girard 4498d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
132 Update FPGA examples with the POP.B bug fix olivier.girard 4511d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4805d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4880d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
37 olivier.girard 5312d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5312d 19h /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5312d 20h /openmsp430/trunk/core/rtl/verilog/register_file.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5433d 22h /openmsp430/trunk/core/rtl/verilog/register_file.v
17 Updated header with SVN info olivier.girard 5459d 17h /openmsp430/trunk/core/rtl/verilog/register_file.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5494d 17h /openmsp430/trunk/core/rtl/verilog/register_file.v

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