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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Rev 200

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200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3418d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
193 Update FPGA projects with latest core RTL changes. olivier.girard 3818d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4139d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4246d 08h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
136 Update all FPGA projects with the latest core version. olivier.girard 4453d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4760d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4814d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4831d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4835d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4872d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5199d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5238d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
37 olivier.girard 5267d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5267d 11h /openmsp430/trunk/core/rtl/verilog/openMSP430.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5267d 11h /openmsp430/trunk/core/rtl/verilog/openMSP430.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5388d 13h /openmsp430/trunk/core/rtl/verilog/openMSP430.v
17 Updated header with SVN info olivier.girard 5414d 09h /openmsp430/trunk/core/rtl/verilog/openMSP430.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5449d 08h /openmsp430/trunk/core/rtl/verilog/openMSP430.v

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