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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [submit.f] - Rev 212

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212 Update all FPGA project examples to support both MSPGCC and TI/RedHat GCC toolchains. olivier.girard 3118d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
202 Add DMA interface support + LINT cleanup olivier.girard 3257d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4246d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
136 Update all FPGA projects with the latest core version. olivier.girard 4453d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4760d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4814d 22h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4831d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
85 Diverse RTL cosmetic updates. olivier.girard 4872d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5199d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
37 olivier.girard 5267d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5277d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5277d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5388d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
16 Updated header with SVN info olivier.girard 5414d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5449d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f

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