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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] [xilinx/] [0_create_bitstream.sh] - Rev 153

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Rev	Log message	Author	Age	Path
153	Update XFLOW scripts to bring more automation. Several bitstreams are now checked in for direct use.	olivier.girard	4341d 14h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/0_create_bitstream.sh
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4855d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5317d 23h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
26	Xilinx implementation example: - update the project directory structure. - make a local copy of the openMSP430 core to make the project self contained.	olivier.girard	5318d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
24	FPGA Setup: Created some BAT files for WINDOWS users.	olivier.girard	5407d 21h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5428d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5489d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/create_bitstream.sh

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