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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] [xilinx/] [scripts/] [openMSP430_fpga.prj] - Rev 153

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153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4324d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/synthesis/xilinx/scripts/openMSP430_fpga.prj
136 Update all FPGA projects with the latest core version. olivier.girard 4476d 09h /openMSP430_fpga.prj
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4783d 09h /openMSP430_fpga.prj
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5222d 10h /openMSP430_fpga.prj
37 olivier.girard 5290d 09h /openMSP430_fpga.prj
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5300d 17h /openMSP430_fpga.prj
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5300d 17h /openMSP430_fpga.prj
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5411d 13h /openMSP430_fpga.prj
16 Updated header with SVN info olivier.girard 5437d 09h /openMSP430_fpga.prj
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5472d 08h /openMSP430_fpga.prj

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