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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 104

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Rev	Log message	Author	Age	Path
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4975d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4981d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4985d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4989d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	5011d 23h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
85	Diverse RTL cosmetic updates.	olivier.girard	5012d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	5017d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	5078d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5165d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5190d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5192d 03h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5339d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
61	Update openMSP430 rtl.	olivier.girard	5371d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5372d 23h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5378d 03h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
40	Minor updates.	olivier.girard	5407d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5407d 00h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
37		olivier.girard	5407d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
36	Remove old core version.	olivier.girard	5407d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5417d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 104

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