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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 109

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Rev	Log message	Author	Age	Path
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4853d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4854d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4869d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4873d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4879d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4883d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4887d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4910d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
85	Diverse RTL cosmetic updates.	olivier.girard	4910d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4915d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4976d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5063d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5088d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5090d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5237d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
61	Update openMSP430 rtl.	olivier.girard	5269d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5271d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
54	Update FPGA projects with the combinatorial loop fixed.	olivier.girard	5276d 19h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
40	Minor updates.	olivier.girard	5305d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
39	Update FPGA projects with new openMSP430 core.	olivier.girard	5305d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 109

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