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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 136

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136 Update all FPGA projects with the latest core version. olivier.girard 4620d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board
132 Update FPGA examples with the POP.B bug fix olivier.girard 4633d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4717d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
112 Modified comment. olivier.girard 4926d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4927d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4981d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4983d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4998d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board
104 Update all FPGA example projects with the latest RTL version. olivier.girard 5002d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 5008d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5012d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 5016d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 5039d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board
85 Diverse RTL cosmetic updates. olivier.girard 5039d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 5044d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5105d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5192d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5217d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board
72 Expand configurability options of the program and data memory sizes. olivier.girard 5219d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5366d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board

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