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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 153

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Rev	Log message	Author	Age	Path
153	Update XFLOW scripts to bring more automation. Several bitstreams are now checked in for direct use.	olivier.girard	4339d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4369d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
149	Update simulation regression result parser. Fixed failing SFR test (due to newer MSPGCC version). Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)	olivier.girard	4372d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4443d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4460d 03h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
136	Update all FPGA projects with the latest core version.	olivier.girard	4491d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4504d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
128	Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 )	olivier.girard	4588d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
112	Modified comment.	olivier.girard	4797d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4798d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4853d 02h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4854d 16h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4869d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4873d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4879d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4883d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4887d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4910d 15h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
85	Diverse RTL cosmetic updates.	olivier.girard	4910d 17h	/openmsp430/trunk/fpga/xilinx_diligent_s3board
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4915d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 153

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