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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board] - Rev 40

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40 Minor updates. olivier.girard 5305d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board
39 Update FPGA projects with new openMSP430 core. olivier.girard 5305d 18h /openmsp430/trunk/fpga/xilinx_diligent_s3board
37 olivier.girard 5305d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board
36 Remove old core version. olivier.girard 5305d 19h /openmsp430/trunk/fpga/xilinx_diligent_s3board
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5316d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5316d 03h /openmsp430/trunk/fpga/diligent_s3board
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5406d 01h /openmsp430/trunk/fpga/diligent_s3board
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5406d 01h /openmsp430/trunk/fpga/diligent_s3board
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5426d 23h /openmsp430/trunk/fpga/diligent_s3board
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5452d 18h /openmsp430/trunk/fpga/diligent_s3board
16 Updated header with SVN info olivier.girard 5452d 19h /openmsp430/trunk/fpga/diligent_s3board
5 Added some ignore pattern properties... olivier.girard 5474d 20h /openmsp430/trunk/fpga/diligent_s3board
3 update FPGA inc file to match the CORE version olivier.girard 5487d 06h /openmsp430/trunk/fpga/diligent_s3board
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5487d 18h /openmsp430/trunk/fpga/diligent_s3board

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