OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk] - Rev 118

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
118 Changelog update (move to modified BSD license). olivier.girard 4767d 20h /openmsp430/trunk
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4767d 20h /openmsp430/trunk
116 Update documentation to reflect the latest core updates. olivier.girard 4783d 21h /openmsp430/trunk
115 Add linker script example. olivier.girard 4792d 20h /openmsp430/trunk
114 Improved the VerifyCPU_ID procedure. olivier.girard 4795d 19h /openmsp430/trunk
113 Created ChangeLog files... olivier.girard 4796d 20h /openmsp430/trunk
112 Modified comment. olivier.girard 4800d 19h /openmsp430/trunk
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4801d 19h /openmsp430/trunk
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4802d 19h /openmsp430/trunk
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4856d 04h /openmsp430/trunk
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4857d 17h /openmsp430/trunk
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4857d 17h /openmsp430/trunk
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4857d 18h /openmsp430/trunk
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4872d 19h /openmsp430/trunk
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4876d 20h /openmsp430/trunk
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4878d 01h /openmsp430/trunk
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4878d 18h /openmsp430/trunk
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4878d 19h /openmsp430/trunk
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4881d 19h /openmsp430/trunk
99 Small fix for CVER simulator support. olivier.girard 4882d 19h /openmsp430/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.