URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_dpram_256x32.v] - Rev 795

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4606d 05h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_256x32.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5197d 14h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_256x32.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5208d 00h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_256x32.v
141	added OpenRISC version rel3	marcus.erlandsson	5269d 12h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_256x32.v
10	or1200 added from or1k subversion repository	unneback	5670d 15h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_dpram_256x32.v