URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [branches/] [or1200_rel3/] [rtl/] [verilog/] [or1200_ic_ram.v] - Rev 795

Rev	Log message	Author	Age	Path
795	Created or1200_rel3 branch from rev 794	olof	4603d 20h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_ic_ram.v
481	OR1200 Update. RTL and spec.	julius	5064d 12h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_ic_ram.v
141	added OpenRISC version rel3	marcus.erlandsson	5267d 03h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_ic_ram.v
10	or1200 added from or1k subversion repository	unneback	5668d 06h	/openrisc/branches/or1200_rel3/rtl/verilog/or1200_ic_ram.v