URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32/] [or32.c] - Rev 116

Rev	Log message	Author	Age	Path
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5145d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/or32.c
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5146d 19h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/or32.c
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5146d 20h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/or32.c
104	Candidate release 0.4.0rc4	jeremybennett	5154d 02h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/or32.c
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5528d 04h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32/or32.c