OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32] - Rev 98

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5186d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5200d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
96 Various changes which had not been picked up in earlier commits. jeremybennett 5201d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
91 Tidy up of some obsolete configuration code. jeremybennett 5213d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5213d 22h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.
jeremybennett 5214d 21h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
80 Add missing configuration files to SVN. jeremybennett 5215d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5545d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc1/cpu/or32

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.