URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [testsuite/] [or1ksim.tests/] [inst-set-test.exp] - Rev 116

Rev	Log message	Author	Age	Path
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5176d 05h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/testsuite/or1ksim.tests/inst-set-test.exp
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5177d 05h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/testsuite/or1ksim.tests/inst-set-test.exp
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5177d 06h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/testsuite/or1ksim.tests/inst-set-test.exp
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5178d 05h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/testsuite/or1ksim.tests/inst-set-test.exp
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5181d 06h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc1/testsuite/or1ksim.tests/inst-set-test.exp