OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2/] [cpu/] [common] - Rev 101

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5184d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
100 Single precision FPU stuff for or1ksim julius 5184d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5190d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5204d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
96 Various changes which had not been picked up in earlier commits. jeremybennett 5205d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
91 Tidy up of some obsolete configuration code. jeremybennett 5218d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5218d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5219d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
80 Add missing configuration files to SVN. jeremybennett 5219d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5549d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/cpu/common

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.