OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2/] [testsuite/] [or1ksim.tests] - Rev 116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5148d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5149d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5149d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5150d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5153d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
106 Removing old tests, pending addition of new ones. jeremybennett 5153d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
104 Candidate release 0.4.0rc4 jeremybennett 5156d 11h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5165d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5171d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5185d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.		 jeremybennett 5188d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5192d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
91 Tidy up of some obsolete configuration code. jeremybennett 5199d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5199d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5200d 03h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2/testsuite/or1ksim.tests

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.