OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc2] - Rev 118

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5145d 01h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5147d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5148d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5148d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5149d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
110 or1ksim make check should work without a libc in the or32-elf tools julius 5150d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5152d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
106 Removing old tests, pending addition of new ones. jeremybennett 5152d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
104 Candidate release 0.4.0rc4 jeremybennett 5155d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5164d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
100 Single precision FPU stuff for or1ksim julius 5164d 08h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
99 Bug in test evaluation for library fixed. jeremybennett 5169d 06h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5170d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5184d 13h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
96 Various changes which had not been picked up in earlier commits. jeremybennett 5185d 15h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.		 jeremybennett 5187d 07h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5191d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
91 Tidy up of some obsolete configuration code. jeremybennett 5198d 04h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5198d 05h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2
89 Tidy up for latest bug fixes. jeremybennett 5198d 12h /openrisc/tags/or1ksim/or1ksim-0.5.0rc2

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.