URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [cpu] - Rev 98

Rev	Log message	Author	Age	Path
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5171d 14h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
97	Updates to test the new JTAG library interface (not yet complete).	jeremybennett	5185d 20h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
96	Various changes which had not been picked up in earlier commits.	jeremybennett	5186d 22h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
91	Tidy up of some obsolete configuration code.	jeremybennett	5199d 11h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5199d 12h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5200d 11h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
80	Add missing configuration files to SVN.	jeremybennett	5200d 15h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5530d 20h	/openrisc/tags/or1ksim/or1ksim-0.5.0rc3/cpu