URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 808

Rev	Log message	Author	Age	Path
808	OR1200: Add DSX bit support to SR. Updated documentation, revision is now 13. http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85	julius	4388d 13h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
642	or1200: add carry, overflow bits, and range exception	julius	4656d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
640	or1200: add l.ext instructions, fix a MAC bug	julius	4656d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
481	OR1200 Update. RTL and spec.	julius	4882d 10h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
401	Fixing find first one (ff1) and find last one (fl1) support in OR1200. Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported instructions table.	julius	4960d 22h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5023d 13h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5073d 20h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5073d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
141	added OpenRISC version rel3	marcus.erlandsson	5085d 01h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v
10	or1200 added from or1k subversion repository	unneback	5486d 04h	/openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v