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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Rev 865

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865 Raise illegal instruction exception when l.ror is not implemented

Instead of throwing an illegal instruction exception when the rotate
instructions are disabled (OR1200_ALU_IMPL_ROTATE is undefined), another
instruction (slr?) was executed instead.

This closes bug 97

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4056d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
859 Execute trapped instruction after breakpoint is removed

Closes bug #104

When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.

Proposed solution:

- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).

- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).

Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org>		 olof 4169d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4416d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
644 or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled julius 4835d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
640 or1200: add l.ext instructions, fix a MAC bug julius 4835d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
401 Fixing find first one (ff1) and find last one (fl1) support in OR1200.

Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table.		 julius 5139d 23h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5189d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5192d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5193d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5202d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5252d 21h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5252d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
141 added OpenRISC version rel3 marcus.erlandsson 5264d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
10 or1200 added from or1k subversion repository unneback 5665d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v

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