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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Rev 358

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Rev	Log message	Author	Age	Path
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5013d 09h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5015d 02h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5023d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5074d 01h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5074d 02h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
141	added OpenRISC version rel3	marcus.erlandsson	5085d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
10	or1200 added from or1k subversion repository	unneback	5486d 10h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v

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