OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Rev 456

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
401	Fixing find first one (ff1) and find last one (fl1) support in OR1200. Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported instructions table.	julius	5127d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5177d 03h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	5179d 11h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
353	OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: "" * or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: "" * or1200/rtl/verilog/or1200_except.v: Verilator public and access comments * orpsocv2/rtl/verilog/components/or1200/or1200_except.v: "" * orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some Verilator related Lint issues fixed. ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and updated RAM model hooks for new RAM. * orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping * orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: "" * orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping, change include and classes for new RAM model. * orpsocv2/bench/sysc/src/OrpsocAccess.cpp: "" or_debug_proxy - fixing sleep and Windows make issues: * or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly * or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated) ORPmon play around, various changes to low level files.	julius	5181d 05h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5189d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
186	OR1200 RTL FPU fix - RF writeback signal working properly again	julius	5240d 04h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5240d 05h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
141	added OpenRISC version rel3	marcus.erlandsson	5251d 09h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v
10	or1200 added from or1k subversion repository	unneback	5652d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.