URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Rev 481

Rev	Log message	Author	Age	Path
481	OR1200 Update. RTL and spec.	julius	4914d 03h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5042d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5055d 06h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
185	Adding single precision FPU to or1200, initial checkin, not fully tested yet	julius	5105d 14h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
142	added OpenRISC version rel3	marcus.erlandsson	5116d 18h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v
10	or1200 added from or1k subversion repository	unneback	5517d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_top.v