OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Rev 481

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
481 OR1200 Update. RTL and spec. julius 5059d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5190d 13h /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5200d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
142 added OpenRISC version rel3 marcus.erlandsson 5262d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v
10 or1200 added from or1k subversion repository unneback 5663d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.