OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [configure] - Rev 185

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5240d 23h /openrisc/trunk/or1ksim/configure
134 Updates for stable release 0.4.0 jeremybennett 5249d 03h /openrisc/trunk/or1ksim/configure
127 New config option to allow l.xori with unsigned operand. jeremybennett 5254d 23h /openrisc/trunk/or1ksim/configure
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5255d 19h /openrisc/trunk/or1ksim/configure
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5255d 23h /openrisc/trunk/or1ksim/configure
122 Added l.ror and l.rori with associated tests. jeremybennett 5256d 19h /openrisc/trunk/or1ksim/configure
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5256d 20h /openrisc/trunk/or1ksim/configure
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5257d 17h /openrisc/trunk/or1ksim/configure
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5259d 20h /openrisc/trunk/or1ksim/configure
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5260d 19h /openrisc/trunk/or1ksim/configure
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5261d 19h /openrisc/trunk/or1ksim/configure
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5264d 20h /openrisc/trunk/or1ksim/configure
104 Candidate release 0.4.0rc4 jeremybennett 5268d 03h /openrisc/trunk/or1ksim/configure
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5276d 21h /openrisc/trunk/or1ksim/configure
99 Bug in test evaluation for library fixed. jeremybennett 5281d 21h /openrisc/trunk/or1ksim/configure
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5282d 22h /openrisc/trunk/or1ksim/configure
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5297d 05h /openrisc/trunk/or1ksim/configure
96 Various changes which had not been picked up in earlier commits. jeremybennett 5298d 06h /openrisc/trunk/or1ksim/configure
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5303d 20h /openrisc/trunk/or1ksim/configure
91 Tidy up of some obsolete configuration code. jeremybennett 5310d 19h /openrisc/trunk/or1ksim/configure

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.