OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [configure.ac] - Rev 227

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5087d 08h /openrisc/trunk/or1ksim/configure.ac
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5094d 00h /openrisc/trunk/or1ksim/configure.ac
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5117d 05h /openrisc/trunk/or1ksim/configure.ac
134 Updates for stable release 0.4.0 jeremybennett 5125d 08h /openrisc/trunk/or1ksim/configure.ac
127 New config option to allow l.xori with unsigned operand. jeremybennett 5131d 05h /openrisc/trunk/or1ksim/configure.ac
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5132d 00h /openrisc/trunk/or1ksim/configure.ac
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5132d 04h /openrisc/trunk/or1ksim/configure.ac
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5133d 01h /openrisc/trunk/or1ksim/configure.ac
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5133d 22h /openrisc/trunk/or1ksim/configure.ac
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5136d 01h /openrisc/trunk/or1ksim/configure.ac
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5138d 01h /openrisc/trunk/or1ksim/configure.ac
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5141d 01h /openrisc/trunk/or1ksim/configure.ac
104 Candidate release 0.4.0rc4 jeremybennett 5144d 09h /openrisc/trunk/or1ksim/configure.ac
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5153d 03h /openrisc/trunk/or1ksim/configure.ac
99 Bug in test evaluation for library fixed. jeremybennett 5158d 03h /openrisc/trunk/or1ksim/configure.ac
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5159d 04h /openrisc/trunk/or1ksim/configure.ac
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5173d 10h /openrisc/trunk/or1ksim/configure.ac
96 Various changes which had not been picked up in earlier commits. jeremybennett 5174d 11h /openrisc/trunk/or1ksim/configure.ac
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5180d 02h /openrisc/trunk/or1ksim/configure.ac
91 Tidy up of some obsolete configuration code. jeremybennett 5187d 00h /openrisc/trunk/or1ksim/configure.ac

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.