OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu] - Rev 116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5130d 21h /openrisc/trunk/or1ksim/cpu
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5131d 21h /openrisc/trunk/or1ksim/cpu
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5131d 22h /openrisc/trunk/or1ksim/cpu
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5132d 21h /openrisc/trunk/or1ksim/cpu
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5135d 22h /openrisc/trunk/or1ksim/cpu
104 Candidate release 0.4.0rc4 jeremybennett 5139d 05h /openrisc/trunk/or1ksim/cpu
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5147d 23h /openrisc/trunk/or1ksim/cpu
100 Single precision FPU stuff for or1ksim julius 5148d 01h /openrisc/trunk/or1ksim/cpu
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5154d 00h /openrisc/trunk/or1ksim/cpu
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5168d 06h /openrisc/trunk/or1ksim/cpu
96 Various changes which had not been picked up in earlier commits. jeremybennett 5169d 08h /openrisc/trunk/or1ksim/cpu
91 Tidy up of some obsolete configuration code. jeremybennett 5181d 21h /openrisc/trunk/or1ksim/cpu
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5181d 22h /openrisc/trunk/or1ksim/cpu
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5182d 21h /openrisc/trunk/or1ksim/cpu
80 Add missing configuration files to SVN. jeremybennett 5183d 01h /openrisc/trunk/or1ksim/cpu
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5513d 06h /openrisc/trunk/or1ksim/cpu

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.