OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] - Rev 224

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5122d 03h /openrisc/trunk/or1ksim/doc
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5128d 18h /openrisc/trunk/or1ksim/doc
202 Adding executed log in binary format capability to or1ksim julius 5134d 22h /openrisc/trunk/or1ksim/doc
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5151d 23h /openrisc/trunk/or1ksim/doc
134 Updates for stable release 0.4.0 jeremybennett 5160d 03h /openrisc/trunk/or1ksim/doc
127 New config option to allow l.xori with unsigned operand. jeremybennett 5165d 23h /openrisc/trunk/or1ksim/doc
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5166d 19h /openrisc/trunk/or1ksim/doc
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5166d 23h /openrisc/trunk/or1ksim/doc
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5167d 20h /openrisc/trunk/or1ksim/doc
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5168d 17h /openrisc/trunk/or1ksim/doc
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5170d 20h /openrisc/trunk/or1ksim/doc
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5172d 19h /openrisc/trunk/or1ksim/doc
110 or1ksim make check should work without a libc in the or32-elf tools julius 5173d 21h /openrisc/trunk/or1ksim/doc
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5175d 20h /openrisc/trunk/or1ksim/doc
104 Candidate release 0.4.0rc4 jeremybennett 5179d 03h /openrisc/trunk/or1ksim/doc
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5187d 21h /openrisc/trunk/or1ksim/doc
100 Single precision FPU stuff for or1ksim julius 5187d 23h /openrisc/trunk/or1ksim/doc
99 Bug in test evaluation for library fixed. jeremybennett 5192d 21h /openrisc/trunk/or1ksim/doc
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5193d 22h /openrisc/trunk/or1ksim/doc
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5208d 05h /openrisc/trunk/or1ksim/doc

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.