OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [version.texi] - Rev 234

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5072d 11h /openrisc/trunk/or1ksim/doc/version.texi
233 New softfloat FPU and testfloat sw for or1ksim julius 5072d 22h /openrisc/trunk/or1ksim/doc/version.texi
230 Changed library interface. Fixed namespace problems with instruction lookup in library.

* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
jeremybennett 5074d 03h /openrisc/trunk/or1ksim/doc/version.texi
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5076d 03h /openrisc/trunk/or1ksim/doc/version.texi
224 Add new library functions and modify existing ones. Change the parameter type enumarations to upper case. New (simplified and corrected) config file parsing. No include files or default sim.cfg. jeremybennett 5076d 10h /openrisc/trunk/or1ksim/doc/version.texi
220 Updated library interface to take a full command line (this will break all old code). Added -q/--quiet and --report-memory-errors flags to command line. Fixed all tests to match this. jeremybennett 5083d 02h /openrisc/trunk/or1ksim/doc/version.texi
202 Adding executed log in binary format capability to or1ksim julius 5089d 06h /openrisc/trunk/or1ksim/doc/version.texi
143 Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). jeremybennett 5106d 07h /openrisc/trunk/or1ksim/doc/version.texi
134 Updates for stable release 0.4.0 jeremybennett 5114d 10h /openrisc/trunk/or1ksim/doc/version.texi
127 New config option to allow l.xori with unsigned operand. jeremybennett 5120d 07h /openrisc/trunk/or1ksim/doc/version.texi
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5121d 02h /openrisc/trunk/or1ksim/doc/version.texi
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5121d 06h /openrisc/trunk/or1ksim/doc/version.texi
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5122d 03h /openrisc/trunk/or1ksim/doc/version.texi
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5123d 00h /openrisc/trunk/or1ksim/doc/version.texi
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5125d 03h /openrisc/trunk/or1ksim/doc/version.texi
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5127d 03h /openrisc/trunk/or1ksim/doc/version.texi
110 or1ksim make check should work without a libc in the or32-elf tools julius 5128d 04h /openrisc/trunk/or1ksim/doc/version.texi
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5130d 03h /openrisc/trunk/or1ksim/doc/version.texi
104 Candidate release 0.4.0rc4 jeremybennett 5133d 11h /openrisc/trunk/or1ksim/doc/version.texi
100 Single precision FPU stuff for or1ksim julius 5142d 07h /openrisc/trunk/or1ksim/doc/version.texi

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.