| Rev |
Log message |
Author |
Age |
Path |
| 434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
5091d 00h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 432 |
Updates to handle interrupts correctly. |
jeremybennett |
5092d 04h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 420 |
New feature to trace instructions (option --trace). Manual updated to match. |
jeremybennett |
5106d 04h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 385 |
Updates for Or1ksim 0.5.0rc2.
* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.
* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected. |
jeremybennett |
5146d 05h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 346 |
Changes to support Or1ksim 0.5.0rc1
Top level changes:
* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
Changes in testsuite:
* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.
Changes in testsuite/test-code-or1k:
* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1. |
jeremybennett |
5171d 07h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 236 |
Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.
* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions. |
jeremybennett |
5205d 03h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 234 |
Minor tidy ups. DOS end of line chars fixed. |
jeremybennett |
5206d 09h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 230 |
Changed library interface. Fixed namespace problems with instruction lookup in library.
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int. |
jeremybennett |
5208d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 143 |
Fix building for Cygwin with GCC 3.4.4 (Bug 1797). Fix breakpoints with instruction cache enabled (Bug 195). |
jeremybennett |
5240d 05h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 134 |
Updates for stable release 0.4.0 |
jeremybennett |
5248d 08h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 127 |
New config option to allow l.xori with unsigned operand. |
jeremybennett |
5254d 05h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 124 |
Overflow handling now in line with architecture manual. Tests added. |
jeremybennett |
5255d 00h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 123 |
Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. |
jeremybennett |
5255d 04h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 122 |
Added l.ror and l.rori with associated tests. |
jeremybennett |
5256d 00h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 121 |
Adds exception handling to l.jalr and l.jr. Adds appropriate tests. |
jeremybennett |
5256d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 118 |
New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. |
jeremybennett |
5256d 22h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 116 |
Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. |
jeremybennett |
5259d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 115 |
Added support for l.fl1 and tests for l.ff1 and l.fl1 |
jeremybennett |
5260d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 114 |
l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. |
jeremybennett |
5260d 02h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
| 112 |
Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. |
jeremybennett |
5261d 01h |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog |
