URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ChangeLog] - Rev 112

Rev	Log message	Author	Age	Path
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5134d 20h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5135d 22h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5137d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
104	Candidate release 0.4.0rc4	jeremybennett	5141d 04h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
98	Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller.	jeremybennett	5156d 00h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
93	Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0.	jeremybennett	5176d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog
90	Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain).	jeremybennett	5183d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog