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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [inst-set-test.S] - Rev 787

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787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.		 jeremybennett 4445d 20h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5093d 12h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5094d 09h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5096d 12h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5101d 12h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S

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