URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [is-add-test.S] - Rev 118

Rev	Log message	Author	Age	Path
118	New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library.	jeremybennett	5116d 21h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5119d 00h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5120d 00h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5120d 01h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5121d 00h	/openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S