OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim] - Rev 457

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4940d 02h /openrisc/trunk/or1ksim
451 More tidying up. jeremybennett 4950d 22h /openrisc/trunk/or1ksim
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4951d 02h /openrisc/trunk/or1ksim
443 Work in progress on more efficient Ethernet. jeremybennett 4956d 07h /openrisc/trunk/or1ksim
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4956d 21h /openrisc/trunk/or1ksim
440 Updated documentation to describe new Ethernet usage. jeremybennett 4957d 22h /openrisc/trunk/or1ksim
437 Or1ksim - ethernet peripheral update, working much better. julius 4965d 17h /openrisc/trunk/or1ksim
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4966d 17h /openrisc/trunk/or1ksim
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4969d 23h /openrisc/trunk/or1ksim
433 New single program interrupt test programs. jeremybennett 4971d 01h /openrisc/trunk/or1ksim
432 Updates to handle interrupts correctly. jeremybennett 4971d 02h /openrisc/trunk/or1ksim
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4973d 23h /openrisc/trunk/or1ksim
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 4974d 03h /openrisc/trunk/or1ksim
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4976d 22h /openrisc/trunk/or1ksim
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4985d 03h /openrisc/trunk/or1ksim
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4985d 06h /openrisc/trunk/or1ksim
387 Fixed testing, to always use our DEJAGNU config. jeremybennett 5025d 03h /openrisc/trunk/or1ksim
386 Updated for release 0.5.0rc2 jeremybennett 5025d 04h /openrisc/trunk/or1ksim
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5025d 04h /openrisc/trunk/or1ksim
376 Adding handling cases for RSP queries seen from new gdb-7.2 in RSP servers in
or1ksim and or_debug_proxy.

Adding ChangeLog to or_debug_proxy		 julius 5032d 09h /openrisc/trunk/or1ksim

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.