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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include] - Rev 52

Rev	Log message	Author	Age	Path
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5406d 09h	/openrisc/trunk/orpsocv2/bench/sysc/include
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5420d 12h	/openrisc/trunk/orpsocv2/bench/sysc/include
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5439d 06h	/openrisc/trunk/orpsocv2/bench/sysc/include
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5490d 16h	/openrisc/trunk/orpsocv2/bench/sysc/include
6	Checking in ORPSoCv2	julius	5553d 04h	/openrisc/trunk/orpsocv2/bench/sysc/include